1. Field of the Invention
The present invention relates to a wafer to wafer structure and method of fabricating the same, and more particularly to a method and structure of coupling interconnects on different wafers using through silicon vias.
2. Description of the Prior Art
With increased requirements for chip density and smaller packaging form factors, advances have been made in three-dimensional integration of circuits. In this technology, devices are stacked, and bonded in the vertical direction. Typically, the stacked devices are electrically coupled by electrical contact pads on the devices.
A current flip-chip technique uses a direct electrical connection of face-down electronic components onto substrates, circuit boards, carriers or the like by means of conductive bumps on the chip bond pads. The flip-chip technique has a drawback in that the production efficiency is poor in terms of process complexity and product cost because it requires conventional solder-using complex connection processes. These are solder flux coating, chip/board arranging, solder bump ref lowing, flux removing, and curing processes.
It is desirable to have a novel method of fabricating stacked devices which involves easier processes.